1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a memory device in the form of a non-volatile random access memory (NVRAM), in which a volatile memory cell, for example, a static RAM(SRAM) cell or dynamic RAM(DRAM) cell, and a non-volatile memory cell using a floating gate circuit element, for example, an electrically erasable and programmable read only memory (EEPROM) cell, are combined on a one-to-one basis on a chip.
Since an NVRAM possesses both a function of an SRAM, i.e., a high speed read/write operation, and a feature of an EEPROM, i.e., non-volatility, it has been utilized in fields in which, even when a power source is OFF, data is not lost but stored, and when the power source is ON, the data can be freely erased and reprogrammed.
2. Description of the Related Art
In the above NVRAM, when the power source is ON, the SRAM carries out a read/write operation in the same way as a conventional SRAM, the data in the SRAM is stored in the EEPROM before the power source is turned OFF, and utilizing the non-volatile characteristic, the data is held therein while the power source is OFF. When the power source is again switched ON, the data in the EEPROM is recalled to the SRAM and the conventional read/write operation carried out. Accordingly, to realize such store and recall operations, a structure of each of the memory cell units including the SRAM cell and EEPROM cell is complicated, and therefore, the space occupied by the cells on the chip is increased, which leads to a lower reliability and degree of integration of the memory device. Therefore, an improvement by an appropriate design of the cell structure is required.
The store operation in the NVRAM is carried out by utilizing a tunnel effect occurring within an oxidation layer formed between a floating gate and a diffused region in the EEPROM cell. In the store operation, a strongly boosted voltage is employed and a portion thereof is applied across a tunnel capacitor representing an equivalent capacitance of the oxidation layer, with the result that positive or negative charges remain on the floating gate. Note, the positive charges correspond to "1" data and the negative charges to "0".
In the known EEPROM cell, several capacitors other than the tunnel capacitor are parasitically formed in a series connection with the tunnel capacitor, which will be described later. Accordingly, when the strongly boosted voltage for storing data into the EEPROM cells is applied to each of the cells, one portion of the voltage is applied across the tunnel capacitor and the other portion thereof is applied across the parasitically formed capacitors. Namely, to carry out the store operation, a voltage higher than the voltage necessary for electrifying the floating gate to store data must be provided as the strongly boosted voltage.
Therefore, when the non-volatile memory cells including floating gate circuit elements are integrated on a substrate, a region for cutting a channel must be made large or a potential barrier at the junction between the diffused region in the substrate and the gate must be made high, so that each element can withstand the application of the strongly boosted voltage. This, however, is detrimental to a high degree of integration and thus not desirable.
Also, when any one of the tunnel capacitor and other parasitically formed capacitors is destroyed, the whole boosted voltage is lowered, and accordingly, a sufficient voltage necessary for storing data cannot be obtained.